Publications

(Last update: 5/30/2020)

Journals


  1. Reoma Matsuo, Shioya Ryota, and Hideki Ando:
    Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline,
    IEEE Computer Architecture Letters, Vol. 18, No. 2, pp. 170-173 (2019).
    DOI: 10.1109/LCA.2019.2952592
  2. Susumu Mashimo, Ryota Shioya, and Koji Inoue:
    VMOR: Microarchitectural Support for Operand Access in an Interpreter,
    IEEE Computer Architecture Letters, Vol. 17, No. 2, pp. 217—220 (2019).
    DOI: 10.1109/LCA.2018.2866243
  3. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Bank-Aware Instruction Scheduler for a Multibanked Register File,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 696—705 (2018).
    DOI: 10.2197/ipsjjip.26.696
  4. Keita Doi, Ryota Shioya, and Hideki Ando:
    Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 445—460 (2018).

International Conferences & Symposiums (with peer review)


  1. Susumu Mashimo, Ryota Shioya, Koji Inoue:
    Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core,
    International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2020), pp. 207-216, Fukuoka, Japan, Jan. 2020.
    DOI: 10.1145/3368474.3368496
  2. Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, and Ryota Shioya:
    An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor,
    IEEE International Conference on Field-Programmable Technology (FPT), pp. 63—71 (2019).
    (Best Paper Candidate)
    PDF
  3. Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, and Shuichi Sakai:
    STRAIGHT: Hazardless Processor Architecture without Register Renaming,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51), pp. 121—133 (2018).
    DOI: 10.1109/MICRO.2018.00019
    PDF
  4. Shinji Sakai, Taishi Suenaga, Ryota Shioya, and Hideki Ando:
    Rearranging Random Issue Queue with High IPC and Short Delay,
    IEEE International Conference on Computer Design (ICCD 36), pp. 123—131 (2018).
    DOI: 10.1109/ICCD.2018.00027
  5. Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Isolation-Safe Speculative Access Control for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 517—520 (2018).
    DOI: 10.1109/ICECS.2018.8618020
  6. Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    An Analysis and a Solution of False Conflicts for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 529—532 (2018).
    DOI: 10.1109/ICECS.2018.8617977
  7. Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode,
    International Conference on Architecture of Computing Systems (ARCS 31) (Springer), pp. 211—224 (2018).
  8. Ushio Jimbo, and Ryota Shioya and Masahiro Goshima:
    Application of Timing Fault Detection to Rocket Core on FPGA,
    International Workshop on Computer Systems and Architectures (CSA), pp. — (2018).