Publications 2018

(Last update: 10/19/2020)

Journals

  1. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Bank-Aware Instruction Scheduler for a Multibanked Register File,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 696—705 (2018).
    DOI: 10.2197/ipsjjip.26.696
  2. Keita Doi, Ryota Shioya, and Hideki Ando:
    Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 445—460 (2018).

International Conferences & Symposiums (with peer review)

  1. Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, and Shuichi Sakai:
    STRAIGHT: Hazardless Processor Architecture without Register Renaming,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51), pp. 121—133 (2018).
    DOI: 10.1109/MICRO.2018.00019
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  2. Shinji Sakai, Taishi Suenaga, Ryota Shioya, and Hideki Ando:
    Rearranging Random Issue Queue with High IPC and Short Delay,
    IEEE International Conference on Computer Design (ICCD 36), pp. 123—131 (2018).
    DOI: 10.1109/ICCD.2018.00027
  3. Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Isolation-Safe Speculative Access Control for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 517—520 (2018).
    DOI: 10.1109/ICECS.2018.8618020
  4. Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    An Analysis and a Solution of False Conflicts for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 529—532 (2018).
    DOI: 10.1109/ICECS.2018.8617977
  5. Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode,
    International Conference on Architecture of Computing Systems (ARCS 31) (Springer), pp. 211—224 (2018).
  6. Ushio Jimbo, and Ryota Shioya and Masahiro Goshima:
    Application of Timing Fault Detection to Rocket Core on FPGA,
    International Workshop on Computer Systems and Architectures (CSA), pp. — (2018).