Publications

(Last update:2/5/2025)
International Conference/Symposium/Workshop (with peer review)

  1. Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    Biotite: A High-Performance Static Binary Translator using Source-Level Information,
    ACM International Conference on Compiler Construction (CC), (to appear).

  2. Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, and Hiroki Honda:
    CACTI-CNFET: An Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors,
    Asia and South Pacific Design Automation Conference (ASP-DAC), (to appear).

  3. Eri Ogawa, Tetsuro Yamazaki, and Ryota Shioya:
    Dynamic Controllability Analysis for Preventing Injection Attacks,
    IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), (to appear).

  4. Soramichi Akiyama, Ryota Shioya, Yuto Miyatake, and Tongxin Yang:
    Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives,
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 1—9 (2024).
    DOI: 10.1109/ISQED60706.2024.10528683

  5. Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    Branch Divergence-Aware Flexible Approximating Technique on GPUs,
    2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), pp. 1—6 (2024).
    DOI: 10.1109/COOLCHIPS61292.2024.10531165

  6. Masayuki Kimura, and Ryota Shioya:
    ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension,
    ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 1—6 (2024).
    DOI: 10.1145/3665314.3670805
    [ OPEN ACCESS ]

  7. Eri Ogawa, Tetsuro Yamazaki, and Ryota Shioya:
    Dynamic Possible Source Count Analysis for Data Leakage Prevention,
    ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes (MPLR), pp. 98—111 (2024).
    DOI: 10.1145/3679007.3685065
    [ OPEN ACCESS ]

  8. Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
    A Sound and Complete Algorithm for Code Generation in Distance-based ISA,
    ACM International Conference on Compiler Construction (CC), pp. 73—84 (2023).
    [ PDF ]

  9. Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
    Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors,
    IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1—16 (2023).
    [ OPEN ACCESS ]

  10. Yuichi Sugiyama, Reoma Matsuo, and Ryota Shioya:
    SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs,
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1—9 (2023).
    [ PDF ]

  11. Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, and Shigeru Chiba:
    Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake?,
    ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pp. 591—614 (2023).
    [ OPEN ACCESS ]

  12. Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
    An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS,
    IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1—5 (2023).

  13. Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, and Hiroki Honda:
    CNFET7: An Open Source Cell Library for 7nm CNFET Technology,
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 763—768 (2023).

  14. Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    T-SKID: Predicting When to Prefetch Separately from Address Prediction,
    Design, Automation and Test in Europe Conference and Exhibition (DATE22), pp. 1393—1398 (2022).
    [ T-SKID source (t-skid_v3.tar.gz) ]
    [ PDF ]

  15. Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
    Compiling and Optimizing Real-world Programs for STRAIGHT ISA,
    IEEE International Conference on Computer Design (ICCD 39), pp. 400—408 (2021).
    [ PDF ]

  16. Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
    Accurate and Fast Performance Modeling of Processors with Decoupled Front-end,
    IEEE International Conference on Computer Design (ICCD 39), pp. 88—92 (2021).
    [ PDF ]

  17. and Soramichi Akiyama and Ryota Shioya:
    The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout,
    ACM/SPEC International Conference on Performance Engineering (ICPE), pp. 125—132 (2021).

  18. Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    D-JOLT: Distant Jolt Prefetcher,
    The 1st Instruction Prefetching Championship (workshop in conjunction with ISCA 2020), pp. 1—4 (2020).

  19. Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
    A High-Performance Out-of-Order Soft Processor Without Register Renaming,
    IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 73—78 (2020).

  20. Susumu Mashimo, Ryota Shioya, and Koji Inoue:
    Energy Efficient Runahead Execution on a Tightly-Coupled Heterogeneous Core,
    International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia), pp. 207—216 (2020).

  21. Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, and Shuichi Sakai and Ryota Shioya:
    T-SKID: Timing Skid Prefetcher,
    The Third Data Prefetching Championship (workshop in conjunction with ISCA 2019), pp. 1—4 (2019).

  22. Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, and Ryota Shioya:
    An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor,
    IEEE International Conference on Field-Programmable Technology (FPT), pp. 63—71 (2019).
    [ PDF ]

  23. Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, and Shuichi Sakai:
    STRAIGHT: Hazardless Processor Architecture without Register Renaming,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51), pp. 121—133 (2018).
    DOI: 10.1109/MICRO.2018.00019
    [ PDF ]

  24. Shinji Sakai, Taishi Suenaga, Ryota Shioya, and Hideki Ando:
    Rearranging Random Issue Queue with High IPC and Short Delay,
    IEEE International Conference on Computer Design (ICCD 36), pp. 123—131 (2018).
    DOI: 10.1109/ICCD.2018.00027

  25. Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Isolation-Safe Speculative Access Control for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 517—520 (2018).
    DOI: 10.1109/ICECS.2018.8618020

  26. Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    An Analysis and a Solution of False Conflicts for Hardware Transactional Memory,
    IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 529—532 (2018).
    DOI: 10.1109/ICECS.2018.8617977

  27. Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode,
    International Conference on Architecture of Computing Systems (ARCS 31) (Springer), pp. 211—224 (2018).

  28. Ushio Jimbo, and Ryota Shioya and Masahiro Goshima:
    Application of Timing Fault Detection to Rocket Core on FPGA,
    International Workshop on Computer Systems and Architectures (CSA), pp. 178—181 (2018).
    DOI: 10.1109/CANDARW.2018.00041

  29. Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Initial Study of a Phase-Aware Scheduling for Hardware Transactional Memory,
    IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim), pp. — (2017).

  30. Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Front-end Execution Architecture for High Energy Efficiency,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 47), pp. 419—431 (2014).
    DOI: 10.1109/MICRO.2014.35
    [ PDF ] [ SLIDE ]

  31. Ryota Shioya, and Hideki Ando:
    Energy Efficiency Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length,
    IEEE International Conference on Computer Design (ICCD 32), pp. 416—423 (2014).
    DOI: 10.1109/ICCD.2014.6974714
    [ PDF ]

  32. Ryota Shioya, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Register Cache System not for Latency Reduction Purpose,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 43), pp. 301—312 (2010).
    DOI: 10.1109/MICRO.2010.43
    [ PDF ] [ SLIDE ]

  33. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Low-overhead architecture for security tag,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 135—142 (2009).
    DOI: 10.1109/PRDC.2009.30

  34. Kunbo Li, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    String-wise information flow tracking against script injection attacks,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 169—176 (2009).
    DOI: 10.1109/PRDC.2009.35

  35. Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Base Address Recognition with Data Flow Tracking for Injection Attack Detection,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2006), pp. 165—172 (2006).

Journal/Transaction/Letter

  1. Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    Flexible Approximate Computing for Mitigating Branch Divergence in GPUs,
    IEEE MICRO, (to appear).

  2. Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    Enhancing GPU Performance through Complexity-Effective Out-of-Order Execution using Distance-based ISA,
    IEICE Transactions on Information and Systems, (to appear).

  3. Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, and Hiroki Honda:
    CNFET-OCL: Open-source Cell Libraries for Advanced CNFET Technologies,
    IEEE Access, (to appear).

  4. Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
    Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores,
    IEEE Computer Architecture Letters (CAL), (to appear).

  5. Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
    A Principal Factor of Performance in Decoupled Front-end,
    IEICE Transactions on Information and Systems, Vol. E106-D, No. 7, pp. 1960—1968 (2023).

  6. Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA,
    IEEE Computer Architecture Letters, Vol. 18, No. 2, pp. 1—4 (2023).
    DOI: 10.1109/LCA.2023.3289317

  7. Soramichi Akiyama, Junji Yamada, and Ryota Shioya:
    Research Trend of Low-latency and Low-power DRAM Technologies that Exploit Design Margins,
    IPSJ Transaction on Advanced Computing Systems, Vol. 16, No. 1, pp. 14—28 (2023).
    (in Japanese)

  8. Yasutaka Matsuda, Ryota Shioya, and Hideki Ando:
    Reducing Energy Consumption of Wakeup Logic through Double-stage Tag Comparison,
    IEICE Transactions on Information and Systems, Vol. E105-D, No. 2, pp. 320—332 (2022).

  9. Reoma Matsuo, Ryota Shioya, and Hideki Ando:
    Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline,
    IEEE Computer Architecture Letters, Vol. 18, No. 2, pp. 170—173 (2019).
    DOI: 10.1109/LCA.2019.2952592

  10. Susumu Mashimo, Ryota Shioya, and Koji Inoue:
    VMOR: Microarchitectural Support for Operand Access in an Interpreter,
    IEEE Computer Architecture Letters, Vol. 17, No. 2, pp. 217—220 (2019).
    DOI: 10.1109/LCA.2018.2866243

  11. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Bank-Aware Instruction Scheduler for a Multibanked Register File,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 696—705 (2018).
    DOI: 10.2197/ipsjjip.26.696

  12. Keita Doi, Ryota Shioya, and Hideki Ando:
    Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 445—460 (2018).

  13. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Skewed Multistaged Multibanked Register File for Area and Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E100-D, No. 4, pp. 822—837 (2017).

  14. Ushio Jimbo, Junji Yamada, Ryota Shioya, and Masahiro Goshima:
    Applying Razor Flip-Flops to SRAM Read Circuits,
    IEICE Transactions on Information and Systems, Vol. E100-C, No. 3, pp. 245—258 (2017).

  15. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology,
    IEICE Transactions on Information and Systems, Vol. E100-C, No. 3, pp. 232—244 (2017).

  16. Ryota Shioya, Ryo Takami, Msahiro Goshima, and Hideki Ando:
    FXA: Executing Instructions in Front-End for Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 4, pp. 1092—1107 (2016).

  17. Ryota Shioya, and Hideki Ando:
    Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 3, pp. 630—640 (2016).

  18. Hideki Ando, and Ryota Shioya:
    Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 2, pp. 341—350 (2015).

  19. Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Address Order Violation Detection with Parallel Counting Bloom Filters,
    IEICE Transactions on Information and Systems, Vol. E98-C, No. 7, pp. 580—593 (2015).

  20. Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, and Shuichi Sakai:
    Register Indirect Jump Target Forwarding,
    IEICE Transactions on Information and Systems, Vol. E96-D, No. 2, pp. 278—288 (2013).
    DOI: 10.1587/transinf.E96.D.278
    [ PDF ]

  21. Shuji Yoshida, Soichiro Hirohata, Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Clocking Scheme Enabling Dynamic Time Borrowing,
    IPSJ Trans. on Advanced Computing Systems, Vol. 6, No. 1, pp. 1—16 (2013).
    (in Japanese)

  22. Masahiro Goshima, Naruki Kurata, Ryota Shioya, and Shuichi Sakai:
    Timing-Fault-Tolerant Out-of-Order Processor,
    IPSJ Trans. on Advanced Computing Systems, Vol. 6, No. 1, pp. 17—30 (2013).
    (in Japanese)

  23. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Low-Overhead Architecture for Security Tag,
    IEICE Transactions on Information and Systems, Vol. E94-D, No. 1, pp. 69—78 (2011).
    DOI: 10.1587/transinf.E94.D.69

  24. Hironori Ichibayashi, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Anti-Dualflow Architecture,
    IPSJ Trans. on Advanced Computing Systems, Vol. 1, No. 2, pp. 22—33 (2008).
    (in Japanese)

  25. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    SWIFT: String-Wise Information Flow Tracking,
    IPSJ Transaction on Advanced Computing Systems, Vol. 1, No. 2, pp. 261—274 (2008).
    (in Japanese)

  26. Ryota Shioya, Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    LRU-based Global Replacement Algorithm for Non-Uniform Shared Cache of Multi-Core Processors,
    IPSJ Transaction on Advanced Computing Systems, Vol. 48, No. SIG3, pp. 59—74 (2007).
    (in Japanese)