Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors,
IEEE/ACM International Symposium on Microarchitecture (MICRO), (to appear).Yuichi Sugiyama, Reoma Matsuo, and Ryota Shioya:
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (to appear).Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, and Shigeru Chiba:
Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake?,
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), (to appear).Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
A Sound and Complete Algorithm for Code Generation in Distance-based ISA,
ACM International Conference on Compiler Construction (CC), pp. 73—84 (2023).
[ PDF ]Matsuo Reoma, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA,
Design, Automation and Test in Europe Conference and Exhibition (DATE) (extended abstract), pp. 1—2 (2023).Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, and Masahiro Goshima:
Out-of-Step Pipeline for Gather/Scatter Instructions,
Design, Automation and Test in Europe Conference and Exhibition (DATE) (extended abstract), pp. 1—2 (2023).Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, and Hiroki Honda:
CNFET7: An Open Source Cell Library for 7nm CNFET Technology,
Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 763—768 (2023).Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
T-SKID: Predicting When to Prefetch Separately from Address Prediction,
Design, Automation and Test in Europe Conference and Exhibition (DATE22), pp. 1393—1398 (2022).
[ T-SKID source (t-skid_v3.tar.gz) ]
[ PDF ]Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
Compiling and Optimizing Real-world Programs for STRAIGHT ISA,
IEEE International Conference on Computer Design (ICCD 39), pp. 400—408 (2021).
[ PDF ]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, and Shuichi Sakai:
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end,
IEEE International Conference on Computer Design (ICCD 39), pp. 88—92 (2021).
[ PDF ]and Soramichi Akiyama and Ryota Shioya:
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout,
ACM/SPEC International Conference on Performance Engineering (ICPE), pp. 125—132 (2021).Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
D-JOLT: Distant Jolt Prefetcher,
The 1st Instruction Prefetching Championship (workshop in conjunction with ISCA 2020), pp. 1—4 (2020).Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
A High-Performance Out-of-Order Soft Processor Without Register Renaming,
IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 73—78 (2020).Susumu Mashimo, Ryota Shioya, and Koji Inoue:
Energy Efficient Runahead Execution on a Tightly-Coupled Heterogeneous Core,
International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia), pp. 207—216 (2020).Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, and Shuichi Sakai and Ryota Shioya:
T-SKID: Timing Skid Prefetcher,
The Third Data Prefetching Championship (workshop in conjunction with ISCA 2019), pp. 1—4 (2019).Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, and Ryota Shioya:
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor,
IEEE International Conference on Field-Programmable Technology (FPT), pp. 63—71 (2019).
[ PDF ]Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, and Shuichi Sakai:
STRAIGHT: Hazardless Processor Architecture without Register Renaming,
IEEE/ACM International Symposium on Microarchitecture (MICRO 51), pp. 121—133 (2018).
DOI: 10.1109/MICRO.2018.00019
[ PDF ]Shinji Sakai, Taishi Suenaga, Ryota Shioya, and Hideki Ando:
Rearranging Random Issue Queue with High IPC and Short Delay,
IEEE International Conference on Computer Design (ICCD 36), pp. 123—131 (2018).
DOI: 10.1109/ICCD.2018.00027Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
Isolation-Safe Speculative Access Control for Hardware Transactional Memory,
IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 517—520 (2018).
DOI: 10.1109/ICECS.2018.8618020Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory,
IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), pp. 529—532 (2018).
DOI: 10.1109/ICECS.2018.8617977Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, and Hideki Ando:
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode,
International Conference on Architecture of Computing Systems (ARCS 31) (Springer), pp. 211—224 (2018).Ushio Jimbo, and Ryota Shioya and Masahiro Goshima:
Application of Timing Fault Detection to Rocket Core on FPGA,
International Workshop on Computer Systems and Architectures (CSA), pp. 178—181 (2018).
DOI: 10.1109/CANDARW.2018.00041Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
Initial Study of a Phase-Aware Scheduling for Hardware Transactional Memory,
IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim), pp. — (2017).Ryota Shioya, Masahiro Goshima, and Hideki Ando:
A Front-end Execution Architecture for High Energy Efficiency,
IEEE/ACM International Symposium on Microarchitecture (MICRO 47), pp. 419—431 (2014).
DOI: 10.1109/MICRO.2014.35
[ PDF ] [ SLIDE ]Ryota Shioya, and Hideki Ando:
Energy Efficiency Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length,
IEEE International Conference on Computer Design (ICCD 32), pp. 416—423 (2014).
DOI: 10.1109/ICCD.2014.6974714
[ PDF ]Ryota Shioya, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
Register Cache System not for Latency Reduction Purpose,
IEEE/ACM International Symposium on Microarchitecture (MICRO 43), pp. 301—312 (2010).
DOI: 10.1109/MICRO.2010.43
[ PDF ] [ SLIDE ]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
Low-overhead architecture for security tag,
IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 135—142 (2009).
DOI: 10.1109/PRDC.2009.30Kunbo Li, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
String-wise information flow tracking against script injection attacks,
IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 169—176 (2009).
DOI: 10.1109/PRDC.2009.35Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection,
IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2006), pp. 165—172 (2006).